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1 of 32 092800 features incorporates industry standard ds1287 pc clock plus enhanced features: +3- or +5v operation 64-bit silicon serial number 64-bit customer specific rom or additional serial number available power control circuitry supports system power-on from date/time alarm or key closure automatic battery backup and write protection to external sram crystal select bit allows rtc to operate with 6 pf or 12.5 pf crystal 114 bytes user nv ram auxiliary battery input ram clear input century register 32 khz output for power management 32-bit v cc powered elapsed time counter 32-bit v bat powered elapsed time counter 16-bit power cycle counter compatible with existing bios for original ds1287 functions available as ic (ds1689) or standalone module with embedded battery and crystal (DS1693) ic is available in industrial temperature version timekeeping algorithm includes leap year compensation valid up to 2100 ordering information part # description ds1689s rtc ic, 28-pin soic ds1689sn rtc ic, 28-pin soic ind DS1693 rtc module; 28-pin dip pin assignment pin description x1 - crystal input x2 - crystal output rclr - ram clear input ad0-ad7 - mux?ed address/data bus pwr - power-on interrupt output (open drain) ks - kickstart input cs - rtc chip select input ale - rtc address strobe wr - rtc write data strobe rd - rtc read data strobe v cco - ram power supply output irq - interrupt request output (open drain) sqw - square wave output v cci - +3- or +5v main supply gnd - ground v bat - battery + supply v baux - auxiliary battery supply psel - +3- or +5v power select cei - ram chip enable in ceo - ram chip enable out ds1689/DS1693 3-volt/5-volt serialized real-time clock with nv ram control www.maxim-ic.com v bau x ds1689s 28-pin soic (330-mil) 13 27 1 2 3 4 5 6 7 8 9 10 11 12 14 28 26 25 24 23 22 21 20 19 18 17 15 16 cei v cco sqw v bat irq psel rd gnd wr a le ks cs ceo v cci x2 ad0 ad2 ad3 ad4 ad5 ad6 ad7 gnd pwr x1 rclr ad1 gnd DS1693 28-pin encapsulated package (740-mil) 13 27 nc ad0 ad2 ad3 ad4 ad5 ad6 ad7 gnd pwr cei v cco sqw nc irq psel rd nc wr a le ks cs 1 2 3 4 5 6 7 8 9 10 11 12 14 28 26 25 24 23 22 21 20 19 18 17 15 16 nc rclr ad1 v bau x ceo v cci
ds1689/DS1693 2 of 32 description the ds1689/DS1693 is a real time cloc k (rtc) designed as a successo r to the industry standard ds1285, ds1385, ds1485, and ds1585 pc real time clocks. this device provides the industry standard ds1285 clock function with the new featur e of either +3.0- or +5.0 volt ope ration and automatic backup and write protection to an external sram. the ds1689 also incorporates a numbe r of enhanced features including a silicon serial number, power-on/off control circ uitry, and 114 bytes of user nvsram, power-on elapsed timer, and power cycle counter. each ds1689/DS1693 is individually manufactured with a unique 64-bit serial number as well as an additional 64-bit customer specific rom or serial number. the serial number is programmed and tested at dallas to insure that no two devices are alike. the serial number can be used to electronically identify a system for purposes such as establishment of a ne twork node address or for ma intenance tracking. blocks of available numbers from dallas semiconductor can be reserved by the customer. the serialized rtcs also incorporate power control circuitry, which allows the system to be powered on via an external stimulus, such as a keyboard or by a time and date (wake-up) alarm. the pwr output pin can be triggered by one or either of these events, and can be used to turn on an external power supply. the pwr pin is under software control, so that when a task is complete, the system power can then be shut down. the ds1689/DS1693 incorporates a pow er-on elapsed time counter, a power-on cycle counter, and a battery powered continuous counter. these three count ers provide valuable info rmation for maintenance and warranty requirements. automatic backup and wr ite protection for an external sram is provided through the v cco and ceo pins. the lithium energy source used to permanently power the real time clock is also used to retain ram data in the absence of v cc power through the v cco pin. the chip enable output to ram ( ceo ) is controlled during power transients to prevent data corruption. the ds1689 is a clock/calendar chip with the features described above . an external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power. the DS1693 incorporates the ds1689 chip, a 32.768 khz cr ystal, and a lithium battery in a complete, self-contained timekeeping module. the entire unit is fully tested at dallas semiconductor such that a minimum of 10 years of timekeeping and data retention in the absence of v cc is guaranteed. operation the block diagram in figure 1 shows the pin connec tions with the major internal functions of the ds1689/DS1693. the following paragraphs de scribe the function of each pin. signal descriptions gnd, v cci - dc power is provided to the device on these pins. v cci is the +3-volt or +5-volt input. five-volt operation is selected when the psel pin is at a logic 1. if psel is floated or at a logic 0, the device will be in auto-sense mode and will determine the correct operating voltage based on the v cci voltage level. psel (power select input) - this pin selects whether 3-volt operation or 5-volt operation will be used. when psel is a logic 1, 5-volt operation is selected. wh en psel is a logic 0 or is floated, the device will be in auto-sense mode and will determine the correct mode of operation based on the voltage on v cci .
ds1689/DS1693 3 of 32 v cco (external sram power supply output) - this pin will be internally connected to v cci when v cci is within nominal limits. however, during power fail, v cco will be internally connected to the v bat or v baux (whichever is larger). for 5-volt operation, switch over from v cci to the backup supply occurs when v cci drops below the larger of v bat and v baux . for 3-volt operation, switch over from v cci to the backup supply occurs at v pf if v pf is less than v bat and v baux . if v pf is greater than v bat and v baux , the switch from v cci to the backup supply occurs when v cci drops below the larger of v bat and v baux . ds1689/DS1693 block diagram figure 1 sqw (square wave output) - the sqw pin can output a signal fro m one of 13 taps provided by the 15 internal divider stages of the real time clock. the frequency of the sqw pin can be changed by programming register a as shown in table 2. the sqw signal can be turned on and off using the sqwe bit in register b. a 32 khz sqw signal is out put when sqwe=1, the enable 32 khz (e32k) bit in extended register 04bh is a logic 1, and v cc is above v pf . a 32 khz square wave is also available when v cc is less than v pf if e32k=1, abe=1, and vo ltage is applied to v baux .
ds1689/DS1693 4 of 32 ad0-ad7 (multiplexed bi-directional address/data bus) - multiplexed buses save pins because address information and data information time-share the same signal paths. the addresses are present during the first portion of the bus cycle and the same pi ns and signal paths are used for data in the second portion of the cycle. address/data multiplexing does not slow the access time of the ds1689 since the bus change from address to data occurs during the internal ram access time. addresses must be valid prior to the latter portion of ale, at which time the ds 1689/DS1693 latches the address. valid write data must be present and held stable during the latter portion of the wr pulse. in a read cycle the ds1689/DS1693 outputs 8 bits of data durin g the latter portion of the rd pulse. the read cycle is terminated and the bus returns to a high impedance state as rd transitions high. the address/da ta bus also serves as a bi- directional data path for the external extended ram. ale (rtc address strobe input; active high) - a pulse on the address strobe pin serves to demultiplex the bus. the falling edge of ale causes the rtc address to be latched within the ds1689/DS1693. rd (rtc read input; active low) - rd identifies the time period when the ds1689/DS1693 drives the bus with rtc read data. the rd signal is an enable signal fo r the output buffers of the clock. wr (rtc write input; active low) - the wr signal is an active low signal. the wr signal defines the time period during which data is written to the addressed register. cs (rtc chip select input; active low) - the chip select signal must be asserted low during a bus cycle for the rtc portion of the ds1689/DS1693 to be accessed. cs must be kept in the active state during rd and wr timing. bus cycles, which take place with ale asserted but without asserting, cs will latch addresses. however, no data transfer will occur. irq (interrupt request output; open drain, active low) - the irq pin is an active low output of the ds1689/DS1693 that can be tied to the in terrupt input of a processor. the irq output remains low as long as the status bit causing the interrupt is pres ent and the corresponding interrupt-enable bit is set. to clear the irq pin, the application software must clear all enabled flag bits contributing to irq ?s active state. when no interrupt conditions are present, the irq level is in the high impedance state. multiple interrupting devices can be connected to an irq bus. the irq pin is an open drain output and requires an external pull-up resistor. cei (ram chip enable input; active low) - cei should be driven low to enable the external ram. ceo (ram chip enable output; active low) - when power is valid, ceo will equal cei . when power is not valid, ceo will be driven high regardless of cei . pwr (power-on output; open drain, active low) - the pwr pin is intended for use as an on/off control for the system power. with v cc voltage removed from the ds1689/DS1693, pwr may be automatically activated from a kickstart input via the ks pin or from a wake-up interrupt. once the system is powered on, the state of pwr can be controlled via bits in the dallas registers.
ds1689/DS1693 5 of 32 ks (kickstart input; active low) - when v cc is removed from the ds1689/DS1693, the system can be powered on in response to an active low transition on the ks pin, as might be generated from a key closure. v baux must be present and auxiliary battery enable bit (abe) must be set to 1 if the kickstart function is used, and the ks pin must be pulled up to the v baux supply. while v cc is applied, the ks pin can be used as an interrupt input. rclr (ram clear input; active low) - if enabled by software, taking rclr low will result in the clearing of the 114 bytes of user ram. when enabled, rclr can be activated whether or not v cc is present. v baux - auxiliary battery input required for kickstart and wake-up features. this input also supports clock/calendar and external nvram if v bat is at lower voltage or is not present. a standard +3-volt lithium cell or other energy source can be used. battery voltage must be held between +2.5 and +3.7 volts for proper operation. if v baux is not going to be used it should be grounded and auxiliary battery enable bit bank 1, register 4bh, should=0. ds1689 only x1, x2 - connections for a standard 32.768 khz quartz cr ystal. for greatest accuracy, the ds1689 must be used with a crystal that has a specified load cap acitance of either 6 pf or 12.5 pf. the crystal select (cs) bit in extended control register 4b is used to select operation with a 6 pf or 12.5 pf crystal. the crystal is attached directly to the x1 and x2 pins. there is no need for external capacitors or resistors. note: x1 and x2 are very high impedance nodes. it is recommended that they and the crystal by guard- ringed with ground and that high frequency si gnals be kept away from the crystal area. for more information on crystal selection and crysta l layout considerations, please consult application note 58, ?crystal considerations w ith dallas real time clocks.? the ds1689 can also be driven by an external 32.768 khz oscillator. in this configuration, the x1 pin is conn ected to the external oscillator signal and the x2 pin is floated. v bat - battery input for any standard 3-volt lithium cell or other energy source. battery voltage must be held between 2.5 and 3.7 volts for proper operation. power-down/power-up considerations the real-time clock function will continue to operate and all of the ram, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the v cci input. when v cci is applied to the ds1689/DS1693 and reaches a level of greater than v pf (power fail trip point), the device becomes accessible after t rec , provided that the oscillator is running and the oscillator countdown chain is not in reset (see register a). this time period allows the system to stabilize after power is applied. when psel is floating or logic 0, the ds1689 is in autosense mode and 3- volt or 5-volt operation is determined based on the voltage on v cci . selection of 5-volt operation is automatically invoked when v cci rises above 4.5 volts for a minimum of t rec . however, 3-volt operation is automatically selected if v cci does not rise above the level of 4.25 volts. sel ection of the power supply input levels requires 150 ms of input stability before operation can commence.
ds1689/DS1693 6 of 32 when 5-volt operation is selected, the device is fully accessible and data can be written and read only when v cci is greater than 4.5 volts. when v cci is below 4.5 volts, read and writes are inhibited. however, the timekeeping function continues unaffect ed by the lower input voltage. as v cc falls below the greater of v bat and v baux , the ram and timekeeper are switched over to a lithium battery connected either to the v bat pin or v baux pin. when 3-volt operation is selected and applied within normal limits, the device is fully accessible and data can be written or read. when v cci falls below v pf , access to the device is inhibited. if v pf is less than v bat and v baux , the power supply is switched from v cci to the backup supply (the greater of v bat and v baux ) when v cci drops below v pf . if v pf is greater than v bat and v baux , the power supply is switched from v cci to the backup supply when v cci drops below the larger of v bat and v baux . when v cc falls below v pf , the chip is write-protected. with the possible exception of the ks , pwr , and sqw pins, all inputs are ignored and a ll outputs are in a high impedance state. rtc address map the address map for the rtc registers of the ds 1689/DS1693 is shown in figure 2. the address map consists of the 14-clock/calendar registers. ten registers contain the time, calendar, and alarm data, and four bytes are used for control and status. all registers can be directly written or read except for the following: 1. registers c and d are read-only. 2. bit 7 of register a is read-only. 3. the high order bit of the seconds byte is read-only. ds1689 real time clock address map figure 2
ds1689/DS1693 7 of 32 time, calendar and alarm locations the time and calendar information is obtained by reading the appropriate register bytes shown in table 1. the time, calendar, and alarm are set or initialized by writing the appropriate register bytes. the contents of the time, calendar, and alarm registers can be either binary or binary-coded decimal (bcd) format. table 1 shows the binary and bcd formats of the twelve time, calendar, and alarm locations that reside in both bank 0 and in bank 1, plus the two extended regist ers that reside in bank 1 only (bank 0 and bank 1 switching will be explained later in this text). before writing the internal time, calendar, and alarm re gisters, the set bit in register b should be written to a logic 1 to prevent updates from occurring while ac cess is being attempted. al so at this time, the data format (binary or bcd) should be set via the data m ode bit (dm) of register b. all time, calendar, and alarm registers must use the same data mode. the se t bit in register b should be cleared after the data mode bit has been written to allow the real- time clock to update the time and calendar bytes. once initialized, the real-time clock makes all updates in the selected mode. the data mode cannot be changed without reinitializing the 10 data bytes. th e 24/12 bit cannot be changed without reinitializing the hour locations. when the 12-hour format is select ed, the high order bit of the hours byte represents pm when it is a logic 1. the time, calendar, and alarm bytes are always accessible because they are double-buffered. once per second the 10 bytes are advanced by one second and checked for an alarm condition. if a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. th e probability of reading incorrect time and calendar data is low. severa l methods of avoiding any possible incorrect time and calendar reads are covered later in this text. the 4 alarm bytes can be used in two ways. first, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. the second use condition is to insert a ?don?t care? state in one or more of the 4 alarm bytes. the ?don?t care? code is any hexadec imal value from c0 to ff. the 2 most significant bits of each byte set the ?don?t care? condition when at logic 1. an alarm will be generated each hour when the ?don?t care? bits are set in the hours byte. similarl y, an alarm is generated every minute with ?don?t care? codes in the hours and minute alarm bytes. the ?don?t care? codes in all 3-alarm bytes create an interrupt every second. the 3 alarm bytes may be used in conjunction with the da te alarm as described in the wakeup/kickstart section. the century count er will be discussed later in this text.
ds1689/DS1693 8 of 32 time, calendar and alarm data modes table 1 range address location function decimal range binary data mode bcd data mode 00h seconds 0-59 00-3b 00-59 01h seconds alarm 0-59 00-3b 00-59 02h minutes 0-59 00-3b 00-59 03h minutes alarm 0-59 00-3b 00-59 hours 12-hr mode 1-12 01-0c am, 81-8c pm 01-12 am, 81-92 pm 04h hours 24-hr mode 0-23 00-17 00-23 hours alarm 12-hr mode 1-12 01-0c am, 81-8c pm 01-12 am, 81-92 pm 05h hours alarm 24-hr mode 0-23 00-17 00-23 06h day of week sunday=1 1-7 01-07 01-07 07h date of month 1-31 01-1f 01-31 08h month 1-12 01-0c 01-12 09h year 0-99 00-63 00-99 bank1, 48h century 0-99 00-63 00-99 bank 1, 49h date alarm 1-31 01-1f 01-31 control registers the four control registers; a, b, c, and d reside in both bank 0 and bank 1. these registers are accessible at all times, even during the update cycle. nonvolatile ram - rtc the 114 general-purpose nonvolatile ram bytes are not dedicated to any special function within the ds1689/DS1693. they can be used by the applicati on program as nonvolatile memory and are fully available during the update cycle. this memory is directly accessible when bank 0 is selected. interrupt control the ds1689/DS1693 includes six separate, fully auto matic sources of interrupt for a processor: 1. alarm interrupt 2. periodic interrupt 3. update-ended interrupt 4. wake-up interrupt 5. kickstart interrupt 6. ram clear interrupt the conditions, which generate each of these indepe ndent interrupt conditions, are described in greater detail elsewhere in this data sheet. this section describes the overall control of the interrupts.
ds1689/DS1693 9 of 32 the application software can select which interrupts, if any are to be used. there are a total of 6 bits including 3 bits in register b and 3 bits in extende d register b which enable the interrupts. the extended register locations are described later. writing a logic 1 to an interrupt enable bit permits that interrupt to be initiated when the event occurs. a logic 0 in the interrupt enable bit prohibits the irq . pin from being asserted from that interrupt conditi on. if an interrupt flag is already set when an interrupt is enabled, irq will immediately be set at an active level, even t hough the event initiating the interrupt condition may have occurred much earlier. as a result, there ar e cases where the software should clear these earlier generated interrupts before first enabling new interrupts. when an interrupt event occurs, the relating flag bit is set to a logic 1 in register c or in extended register a. these flag bits are set regardless of the setting of the corresponding enable bit located either in register b or in extended register b. the flag b its can be used in a polling mode without enabling the corresponding enable bits. however, care should be taken when using the flag bits of register c as they are automatically cleared to 0 immediately after they are read. double latching is imp lemented on these bits so that bits which are set remain stable throughout the read cycle. all bits wh ich were set are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed. one, 2, or 3 bits can be set when reading register c. each utilized flag bit should be examined when read to ensure that no interrupts are lost. the flag bits in extended register a are not automatically cleared following a read. instead, each flag bit can be cleared to 0 only by writing 0 to that bit. when using the flag bits with fully enabled interrupts, the irq line will be driven low when an interrupt flag bit is set and its corresponding enable bit is also set. irq will be held low as long as at least one of the six possible interrupt sources has it s flag and enable bits both set. the irqf bit in register c is a 1 whenever the irq pin is being driven low as a result of one of the six possible active sources. therefore, determination that the ds1689/DS1693 initiated an interrupt is accomplis hed by reading register c and finding irqf=1. irqf will remain set until all enabled interrupt flag bits are cleared to 0. square wave output selection the sqw pin can be programmed to output a vari ety of frequencies divided down from the 32.768 khz crystal tied to x1 and x2. the square wave output is enabled and disabled via the sqwe bit in register b. if the square wave is enabled (sqwe=1), then the output frequency will be determined by the settings of the e32k bit in extended register b and by the rs3-0 bits in register a. if the e32k = 1, then a 32.768 khz square wave will be output on the sq w pin regardless of the settings of rs3-0. if e32k = 0, then the square wave output frequency is determined by the rs3-0 bits. these bits control a 1-of-15 decoder, which selects one of 13 taps that divide th e 32.768 khz frequency. the rs3-0 bits establish the sqw output frequency as shown in tabl e 2. in addition, rs3-0 bits control the periodic interrupt selection as described below. if sqwe1, e32k=1, and the auxiliary battery enable bit (abe, bank 1; register 04bh) is enabled, and voltage is applied to v baux then the 32 khz square wave output signal will be output on the sqw pin in the absence of v cc . this facility is provided to clock external power management circuitry. if any of the above requirements are not met, no square wave output signal will be generated on the sqw pin in the absence of v cc .
ds1689/DS1693 10 of 32 a pattern of 01x in the dv2, dv1, and dv0, bits respectively, will turn the oscillator on and enable the countdown chain. note that this is different than the ds1287, which required a pattern of 010 in these bits. dv0 is now a ?don?t care? because it is used fo r selection between register banks 0 and 1. a pattern of 11x will turn the oscillator on, but the oscillator?s countdown chain will be held in reset, as it was in the ds1287. any other bit combination for dv2 and dv1 will keep the oscillator off. periodic interrupt selection the periodic interrupt will cause the irq pin to go to an active state from once every 500 ms to once every 122 s. this function is separate from the alar m interrupt which can be output from once per second to once per day. the periodic interrupt rate is selected using the same rs3-0 bits in register a which select the square wave frequency (see table 2). changing the bits affects both the square wave frequency and the periodic interrupt output. however, ea ch function has a separate enable bit in register b. the sqwe bit controls the square wave output. similarly, the periodic interrupt is enabled by the pie bit in register b. the periodic interrupt can be us ed with software counters to measure inputs, create output intervals, or await the next needed software function. update cycle the serialized rtc executes an update cycle once pe r second regardless of the set bit in register b. when the set bit in register b is set to 1, the us er copy of the double-buffered time, calendar, alarm and elapsed time byte is frozen and will not update as the time increments. however, the time countdown chain continues to update the internal copy of th e buffer. this feature allows the time to maintain accuracy independent of reading or writing the time, cal endar, and alarm buffers and also guarantees that time and calendar information is consistent. the update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a ?don?t ca re? code is present in all three positions. there are three methods that can handle access of the real-time clock that avoid any possibility of accessing inconsistent time and calendar data. the first method us es the update-ended interrupt. if enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read valid time and date informa tion. if this interrupt is used, the ir qf bit in register c should be cleared before leaving the interrupt routine. a second method uses the update-in-progress bit (uip) in register a to determine if the update cycle is in progress. the uip bit will pulse onc e per second. after the uip bit goes high, the update transfer occurs 244 s later. if a low is read on the uip bit, the user has at least 244 s before the time/calendar data will be changed. therefore, the user should avoid interr upt service routines that would cause the time needed to read valid time/calendar data to exceed 244 s.
ds1689/DS1693 11 of 32 periodic interrupt rate and square wave output frequency table 2 ext. reg. b select bits register a e32k rs3 rs2 rs1 rs0 t pi periodic interrupt rate sqw output frequency 0 0000none none 0 0001 3.90625 ms 256 hz 0 0010 7.8125 ms 128 hz 0 0011 122.070 s 8.192 khz 0 0100 244.141 s 4.096 khz 0 0101 488.281 s 2.048 khz 0 0110 976.5625 s 1.024 khz 0 0111 1.953125 ms 512 hz 0 1000 3.90625 ms 256 hz 0 1001 7.8125 ms 128 hz 0 1010 15.625 ms 64 hz 0 1011 31.25 ms 32 hz 0 1100 62.5 ms 16 hz 0 1101 125 ms 8 hz 0 1110 250 ms 4 hz 0 1111 500 ms 2 hz 1 xxxx* 32.768 khz *rs3-rs0 determine periodic interr upt rates as listed for e32k=0. the third method uses a periodic interrupt to determin e if an update cycle is in progress. the uip bit in register a is set high between the setting of the pf bit in register c (see figure 3). periodic interrupts that occur at a rate of greater than t buc allow valid time and date information to be reached at each occurrence of the periodic interrupt. th e reads should be complete within (t pi / 2+t buc ) to ensure that data is not read during the update cycle. update-ended and periodic interrupt relationship figure 3
ds1689/DS1693 12 of 32 register a msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 uip - the update in progress (uip) bit is a status flag that can be monitored. when the uip bit is a 1, the update transfer will soon occur. when uip is a 0, th e update transfer will not occur for at least 244 ms. the time, calendar, and alarm information in ram is fully available for access when the uip bit is 0. the uip bit is read-only. writing the set bit in register b to a one inhibits any update transfer and clears the uip status bit. dv0, dv1, dv2 - these bits are defined as follows: dv2 = countdown chain 1 - resets countdown chain only if dv1=1 0 - countdown chain enabled dv1 = oscillator enable 0 - oscillator off 1 - oscillator on dv0 = bank select 0 - original bank 1 - extended registers a pattern of 01x is the only combination of bits that will turn the oscillator on and allow the rtc to keep time. a pattern of 11x will enable the oscillator but holds the countdow n chain in reset. the next update will occur at 500 ms after a pattern of 01x is written to dv2, dv1, and dv0. rs3, rs2, rs1, rs0 - these four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. the tap se lected can be used to generate an output square wave (sqw pin) and/or a periodic interrupt. the user can do one of the following: enable the interrupt with the pie bit; enable the sqw output pin with the sqwe bit; enable both at the same time and the same rate; or enable neither. table 2 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the rs bits.
ds1689/DS1693 13 of 32 register b msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set pie aie uie sqwe dm 24/12 dse set - when the set bit is a 0, the update transfer fu nctions normally by advancing the counts once per second. when the set bit is written to a 1, any update transfer is inhibited a nd the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. read cycles can be executed in a similar manner. set is a read/write bit that is not modified by internal functions of the ds1689/DS1693. pie - the periodic interrupt enable bit is a read/write bit which allows the periodic interrupt flag (pf) bit in register c to drive the irq pin low. when the pie bit is set to 1, periodic interrupts are generated by driving the irq pin low at a rate specified by the rs3-rs 0 bits of register a. a 0 in the pie bit blocks the irq output from being driven by a periodic interrupt, but the periodic flag (pf) bit is still set at the periodic rate. pie is not modifi ed by any internal ds1689/DS1693 functions. aie - the alarm interrupt enable (aie) bit is a read/write bit which, when set to a 1, permits the alarm flag (af) bit in register c to assert irq . an alarm interrupt occurs for each second that the 3 time bytes equal the 3 alarm bytes including a don?t care alarm code of binary 11xxxxxx. when the aie bit is set to 0, the af bit does not initiate the irq signal. the internal func tions of the ds1689/DS1693 do not affect the aie bit. uie - the update ended interrupt enable (uie) bit is a read/write that enables the update end flag (uf) bit in register c to assert irq . the set bit going high clears the uie bit. sqwe - when the square wave enable (sqwe) bit is se t to a 1, a square wave signal at the frequency set by the rate-selection bits rs3 through rs0 and the e32k bit is driven out on the sqw pin. when the sqwe bit is set to 0, the sqw pin is held low. sqwe is a read/write bit. dm - the data mode (dm) bit indicates whether time and calendar information is in binary or bcd format. the dm bit is set by the program to the approp riate format and can be read as required. this bit is not modified by internal functions. a 1 in dm sign ifies binary data while a 0 in dm specifies binary coded decimal (bcd) data. 24/12 - the 24/12 control bit establishes the format of the hours byte. a 1 indicates the 24-hour mode and a 0 indicates the 12-hour mode. this bit is read/write. dse - the daylight savings enable (dse) bit is a r ead/write bit which enable s two special updates when dse is set to 1. on the first sunday in april the time increments from 1:59:59 am to 3:00:00 am. on the last sunday in october when the time first reaches 1:59:59 am it changes to 1:00:00 am. these special updates do not occur when the dse bit is a 0. this bit is not affected by internal functions.
ds1689/DS1693 14 of 32 register c msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irqf pf af uf 0 0 0 0 irqf - the interrupt request flag (irqf) bit is set to a 1 when one or more of the following are true: pf = pie = 1 wf = wie = 1 af = aie = 1 kf = kse = 1 uf = uie = 1 rf = rie = 1 i.e., irqf = (pf pie) + (af aie) + (uf uie) + (wf wie) + (kf kse) + (rf rie) any time the irqf bit is a one, the irq pin is driven low. flag bits pf, af, and uf are cleared after register c is read by the program. pf - the periodic interrupt flag (pf) is a read-only bit wh ich is set to a 1 when an edge is detected on the selected tap of the divider chain. th e rs3 through rs0 bits establish the periodic rate. pf is set to a 1 independent of the state of the pie bit. when both pf and pie are 1s, the irq signal is active and will set the irqf bit. the pf bit is cleared by a software read of register c. af - a one in the alarm interrupt flag (af) bit indicates that the current time has matched the alarm time. if the aie bit is also a 1, the irq pin will go low and a one will appear in the irqf bit. a read of register c will clear af. uf - the update ended interrupt flag (uf) bit is set after each update cycle. when the uie bit is set to 1, the one in uf causes the irqf bit to be a 1, which will assert the irq pin. uf is cleared by reading register c. bit 0 through bit 3 - these are unused bits of the status regi ster c. these bits always read 0 and cannot be written. register d msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt000000 0 vrt - the valid ram and time (vrt) bit indicates the condition of the battery connected to the v bat pin or the battery connected to v baux , whichever is at a higher voltage. this bit is not writable and should always be a 1 when read. if a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc data and ram data are questionable. bit 6 through bit 0 - the remaining bits of register d are not usable. they cannot be written and, when read, they will always read 0.
ds1689/DS1693 15 of 32 extended functions the extended functions provided by the ds1689/DS1693 that are new to the ramified rtc family are accessed via a software controlled bank switching scheme, as illustrated in figure 4. in bank 0, the clock/calendar registers and 50 bytes of user ram are in the same locations as for the ds1287. as a result, existing routines implemented within bios, dos, or application software packages can gain access to the ds1689/DS1693 clock registers with no chan ges. also in bank 0, an extra 64 bytes of ram are provided at addresses just above the original loca tions for a total of 114 directly addressable bytes of user ram. when bank 1 is selected, the clock/calendar registers and the original 50 bytes of user ram still appear as bank 0. however, the dallas registers which provide control and status for the extended functions will be accessed in place of the additional 64 bytes of user ram. the major extended functions controlled by the dallas registers are listed below: 1. silicon revision byte 2. serial number 3. 8-byte customer specific rom or serial number 4. century counter 5. auxiliary battery control/status 6. wake-up 7. kickstart 8. ram clear control/status 9. v cc powered elapsed time counter 10. v bat powered elapsed time counter 11. power-on cycle counter the bank selection is controlled by the state of the dv0 bit in register a. to access bank 0 the dv0 bit should be written to a 0. to access bank 1, dv0 should be written to a 1. register locations designated as reserved in the bank 1 map are reserved for future use by dallas semiconductor. bits in these locations cannot be written and will return a 0 if read.
ds1689/DS1693 16 of 32 ds1689/DS1693 extended regist er bank definition figure 4
ds1689/DS1693 17 of 32 silicon serial number/ customer specific rom a total of 128 bits are available for use as serial num ber/rom. these bits may be used as a 128-bit serial number or as a unique 64-bit serial number and 64-b it customer specific serial number or rom. the unique 64-bit serial number is located in bank 1 regi sters 40h-47h. this serial number is divided into three parts. the first byte in register 40h cont ains a model number to identify the device type and revision of the ds1689/DS1693. registers 41h-46h c ontain a unique binary number. register 47h contains a crc byte used to validate the data in registers 40h-46h. the method used to create the crc byte is proprietary to dallas semiconductor, but can be made available if re quired. typical applications should consider this byte simply as part of the overall unique serial number. all 8 bytes of the serial number are read-only registers. the ds1689/DS1693 is manufactured such that no tw o devices will contain an identical number in locations 41h-47h. blocks of numbers for these lo cations can be reserved by the customer. contact dallas semiconductor for special orde ring information for ds1689/DS1693 w ith reserved blocks of serial numbers. as already mentioned, another 64 bits are available for use as an additional serial number or customer specific rom. these 64 bits are located in bank 1 registers 60h-67h. century counter a register has been added in bank 1, location 48h, to k eep track of centuries. the value is read in either binary or bcd according to the setting of the dm bit. auxiliary battery the v baux input is provided to supply power from an auxiliary battery for the ds1689/DS1693 kickstart, wake-up, and sqw output features in the absence of v cc . this power source must be available in order to use these auxiliary features when no v cc is applied to the device. the auxiliary battery enable (abe; bank 1, register 04bh) bit in extended control register b is used to turn on and off the auxiliary battery for the above functions in the absence of v cc . when set to a 1, v baux battery power is enabled, and when cleared to 0, v baux battery power is disabled to these functions. in the ds1689/DS1693, this auxiliary battery may be used as the primary backup power source for maintaining the clock/calendar, user ram, and extended external ram functions. this occurs if the v bat pin is at a lower voltage than v baux . if the ds1689 is to be backed-up using a single battery with the auxiliary features enabled, then v baux should be used and connected to v bat . if v baux is not to be used, it should be grounded and abe should be cleared to 0. wake-up/kickstart the ds1689/DS1693 incorporates a wake -up feature, which can power the system on at a predetermined date through activation of the pwr output pin. in addition, the kickstar t feature can allow the system to be powered-up in response to a low going transition on the ks pin, without operating voltage applied to the v cc pin. as a result, system power may be applied upon such events as a key closure, or modem ring detect signal. in order to use either the wake- up or the kickstart featur es, the ds1689/DS1693 must have an auxiliary battery connected to the v baux pin and the oscillator must be running and the countdown chain must not be in reset (register a dv2, dv1, dv0 = 01x). if dv2, dv1, and dv0 are not in this required state, the pwr pin will not be driven low in respons e to a kickstart or wakeup condition, while in battery-backed mode. the wake-up feature is controlled through the wake-up interrupt enable bit in ex tended control register b (wie, bank 1, 04bh). setting wie to 1 enables the wake-up feature, clearing wie to 0 disables it.
ds1689/DS1693 18 of 32 similarly, the kickstart feature is controlled through the kickstart interrupt enable bit in extended control register b (kse, bank 1, 04bh). a wake-up sequence will occur as follows: when wake-up is enabled via wie = 1 while the system is powered down (no v cc voltage), the clock/calendar will monito r the current date for a match condition with the date alarm register (bank 1, register 049h). in conjunction with the date alarm register, the hours, minutes, and seconds alarm bytes in the clock/cale ndar register map (bank 0, registers 05h, 03h, and 01h) are also monitored. as a result, a wake-up will occur at the date and time specified by the date, hours, minutes, and seconds alarm register values. this additional alarm will occur regardless of the programming of the aie bit (bank 0, register b, 0bh). when the match condition occurs, the pwr pin will automatically be driven low. this output can be used to turn on the main system power supply which provides v cc voltage to the ds1689/DS1693 as well as the other major components in the system. also at this time, the wake-up flag (wf, bank 1, register 04ah) will be set, indicating that a wake-up condition has occurred. a kickstart sequence will occur when kickstarting is enabled via kse = 1. while the system is powered down, the ks input pin will be monitored for a low going transition of minimum pulse width t kspw . when such a transition is detected, the pwr line will be pulled low, as it is for a wake-up condition. also at this time, the kickstart flag (kf, bank 1, register 04ah) w ill be set, indicating that a kickstart condition has occurred. the timing associated with both the wake-up and kickstarting sequences is illustrated in the wake-up / kickstart timing diagram in the electrical specificati ons section of this data sheet. the timing associated with these functions is divided into 5 intervals, labeled 1-5 on the diagram. the occurrence of either a kickstart or wake-up condition will cause the pwr pin to be driven low, as described above. during interval 1, if the supply voltage on the ds1689/DS1693 v cc pin rises above the 3-volt power-fail level before the power-on timeout period (t poto ) expires, then pwr will remain at the active low level. if v cc does not rise above the 3-volt power fail voltage in this time, then the pwr output pin will be turned off and will return to its high impedance level. in this event, the irq pin will also remain tri-stated. the interrupt flag bit (either wf or kf) associated with the attempted power-on sequence will remain set until cleared by software during a subsequent system power-on. if v cc is applied within the timeout period, then the sy stem power-on sequence will continue as shown in intervals 2-5 in the timing diagram. during interval 2, pwr will remain active and irq will be driven to its active low level, indicating that either wf or kf was set in in itiating the power-on. in the diagram ks is assumed to be pulled up to the v baux supply. also at this time, the pab bit will be automatically cleared to 0 in response to a successful power-on. the pwr line will remain active as long as the pab remains cleared to 0. at the beginning of interval 3, the system proce ssor has begun code execution and clears the interrupt condition of wf and/or kf by writing 0s to both of these control bits. as long as no other interrupt within the ds1689/DS1693 is pending, the irq line will be taken inactive once these bits are reset. execution of the application software may proceed. during this time, both the wake-up and kickstart functions may be used to generate status and inte rrupts. wf will be set in response to a date, hours, and minutes match condition. kf will be set in response to a low going transition on ks . if the associated interrupt enable bit is set (wie and/or kse) then the irq line will driven active low in response to enabled event. in
ds1689/DS1693 19 of 32 addition, the other possible interrupt s ources within the ds1689/DS1693 may cause irq to be driven low. while system power is applied, the on chip logic will always attempt to drive the pwr pin active in response to the enabled kickstart or wake -up condition. this is true even if pwr was previously inactive as the result of power being applied by so me means other than wake-up or kickstart. the system may be powered down under software control by setting the pab bit to a logic 1. this causes the open-drain pwr pin to be placed in a high impedance state, as shown at the beginning of interval 4 in the timing diagram. as v cc voltage decays, the irq output pin will be placed in a high impedance state when v cc goes below v pf . if the system is to be again powered on in response to a wake-up or kickstart, then the both the wf and kf flags should be clear ed and wie and/or kse should be enabled prior to setting the pab bit. during interval 5, the system is fully powere d down. battery backup of the clock calendar and nonvolatile ram is in effect, pwr and irq are tri-stated, and monitoring of wake-up and kickstart takes place. ram clear the ds1689/DS1693 provides a ram clear function for th e 114 bytes of user ram. when enabled, this function can be performed regardless of the condition of the v cc pin. the ram clear function is enabled or disabled vi a the ram clear enable bit (rce; bank 1, register 04bh). when this bit is set to a logic 1, the 114 by tes of user ram will be cleared (all bits set to 1) when an active low transition is sensed on the rclr pin. this action will have no effect on either the clock/calendar settings or upon the contents of the external extended ram. the ram clear flag (rf, bank 1, register 04bh) will be set when the ram clear operation has been completed. if v cc is present at the time of the ram clear and rie=1, the irq line will also be driven low upon completion. the interrupt condition can be cleared by writing a 0 to the rf bit. the irq line will then return to its inactive high level provided there are no other pending interrupts. once the rclr pin is activated, all read/write accesses are locked out for a minimum recover time, specified as t rec in the electrical characteristics section. when rce is cleared to 0, the ram clear function is disabled. the state of the rclr pin will have no effect on the contents of the user ram, and transitions on the rclr pin have no effect on rf. extended control registers two extended control registers are provided to supply controls and st atus information for the extended features offered by the ds1689/DS1693. these are designated as extended control registers a and b and are located in register bank 1, locations 04ah and 04 bh, respectively. the functions of the bits within these registers are described as follows. extended control register 4a msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt2 incr * * pab rf wf kf
ds1689/DS1693 20 of 32 vrt2 - this status bit gives the condition of the auxiliary battery. it is set to a logic 1 condition when the external lithium battery is connected to the v baux . if this bit is read as a logic 0, the external battery should be replaced. incr - increment in progress status bit. this bit is set to a 1 when an increment to the time/date registers is in progress and the alarm checks are being made. incr will be set to a 1 at 122 s before the update cycle starts and will be cleared to 0 at the end of each update cycle. pab - power active bar control bit. when this bit is 0, the pwr pin is in the active low state. this bit can be written to a logic 1 or 0 by the user. if either wf and wie = 1 or kf and kse = 1, the pab bit will be cleared to 0. rf - ram clear flag - this bit will be set to a logic 1 when a high to low transition occurs on the rclr input if rce=1. the rf bit is cleared by writing it to a logic 0. this bit can also be written to a logic 1 to force an interrupt condition. wf ? wake-up alarm flag - this bit is set to 1 when a wake-up alarm condition occurs or when the user writes it to a 1. wf is cleared by writing it to a 0. kf - kickstart flag - this bit is set to a 1 when a kickstart condition occurs or when the user writes it to a 1. this bit is cleared by writing it to a logic 0. extended control register 4b msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 abe e32k cs rce prs rie wie kse abe - auxiliary battery enable. this bit when written to a logic 1 will enable the v baux pin for extended functions. e32k - enable 32,768 output. this bit when written to a logic 1 will enable the 32,768 hz oscillator frequency to be output on the sqw pin provided sqwe=1. cs - crystal select bit. when cs is set to a 0, the os cillator is configured for operation with a crystal that has a 6 pf specified load capacitance. when cs= 1, the oscillator is configured for a 12.5 pf crystal. rce - ram clear enable bit. when set to a 1, this bit enables a low level on pin 4 ( rclr ) to clear all 114 bytes of user ram. when rce = 0, the ram clear function is disabled. prs - pab reset select bit. when set to a 0 the pwr pin will be set hi-z when the ds1689 goes into power-fail. when set to a 1, the pwr pin will remain activ e upon entering power-fail. rie - ram clear interrupt enable. when rie is set to a 1, the irq pin will be driven low when a ram clear function is completed. wie ? wake-up alarm interrupt enable. when v cc voltage is absent and wie is set to a 1, the pwr pin will be driven active low when a wake-up condition o ccurs, causing the wf bit to be set to 1. when v cc is then applied, the irq pin will also be driven low. if wie is set while system power is applied, both
ds1689/DS1693 21 of 32 irq and pwr will be driven low in response to wf being set to 1. when wie is cleared to a 0, the wf bit will have no effect on the pwr or irq pins. kse - kickstart interrupt enable. when v cc voltage is absent and kse is set to a 1, the pwr pin will be driven active low when a kickstart condition occurs ( ks pulsed low), causing the kf bit to be set to 1. when v cc is then applied, the irq pin will also be driven low. if kse is set to 1 while system power is applied, both irq and pwr will be driven low in response to kf being set to 1. when kse is cleared to a 0, the kf bit will have no effect on the pwr or irq pins. * reserved bits. these bits are reserved for future use by dallas semiconductor. they can be read and written, but have no effect on operation. elapsed time counters the ds1689/DS1693 has two 32-bit elapsed time counters, which reside in bank 1 of the rtc registers. to access these counters the dv0 bit in register a must first be set to a logical 1. the v cc powered elapsed time counter resides in regi ster 54h through 57h. the lsb of this counter resides in register 54 and the msb is in 57h. the v cc powered elapsed time counter runs only while the v cci input is within nominal limits. the elapsed time count er is a binary counter that records the number of seconds that have elapsed. the counter can be read or written at the user's discretion. the v bat powered elapsed time counter resides in register 58h through 5bh. the lsb of this counter resides in register 58 and the msb is in 5bh. the v bat powered elapsed time counter runs continually as long as the v bat or v baux pin is within nominal limits regardless of the condition of v cci . the number of seconds that have elapsed is recorded in a binary counter and the counter may be read or written at the user?s discretion. in a typical application the v bat powered elapsed time counter can be used to record the length of time that has elapsed from which the equipment which cont ains the device was first put into service. the v cc powered counter can then be used to record the length of time that v cc power is applied. these functions can be particularly useful for warranty and main tenance information. in addition, battery life can be predicted based on known loading factors. however, it is worth noting that a properly selected battery should power the ds1689/DS1693 and external ram for the useful life of most equipment. power cycle counter the ds1689/DS1693 has a 16-bit power cycl e counter that resides in register 5c and 5d of bank 1. the lsb of this counter resides in 5c and the msb is in 5d. this binary counter is incremented by one count each time v cci power is applied within nominal limits. this counter can be read or written at the user?s discretion.
ds1689/DS1693 22 of 32 absolute maximum ratings* voltage on any pin relativ e to ground -0.3v to +7.0v storage temperature -40c to +70c soldering temperature 260c for 10 seconds (see note 18) see ipc/jedec standard j-std-020a for surface mount devices *this is a stress rating only and func tional operation of the device at th ese or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. operating range range temperature v cc commercial 0c to +70c 3v 10% or 5v 10% industrial -40oc to 85oc 3v 10% or 5v 10% recommended dc operating conditions over the operating range parameter symbol min typ max units notes power supply voltage 5-volt operation v cci 4.5 5.0 5.5 v 1 power supply voltage 3-volt operation v cci 2.7 3.0 4.0 v 1 input logic 1 v ih 2.2 v cc +0.3 v 1 input logic 0 v il -0.3 0.6 v 1 battery voltage v bat 2.5 3.7 v 1 auxiliary battery voltage v baux 2.5 3.7 v 1
ds1689/DS1693 23 of 32 dc electrical characteristics over the operating range (5v) parameter symbol min typ max units notes average v cc power supply current i cc1 7 15 ma 2, 3 cmos standby current ( cs =v cc -0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 a cei input leakage i cei -200 +1 a 15 psel input leakage i psel -1 +200 a 16 output leakage current i ol -1 +1 a 8 output logic 1 voltage (i out = -1.0 ma) v oh 2.4 v output logic 0 voltage (i out = +2.1 ma) v ol 0.4 v output voltage v cco1 v cc -0.3 v4 output current i cco1 85 ma 4 power-fail trip point v pf 4.25 4.37 4.5 v 5 battery switch voltage v sw v bat , v baux v output voltage v cco2 v bat -0.3 v6 output current i cco2 100 a 6 battery leakage osc on i bat1 500 1000 na battery leakage osc off i bat2 50 150 na 17 i/o leakage i lo -1 +1 a 7 pwr output @ 0.4v i olpwr 10.0 ma 1 cei to ceo impedance z ce 60 12
ds1689/DS1693 24 of 32 dc electrical characteristics over the operating range (3v) parameter symbol min typ max units notes average v cc power supply current i cc1 5 10 ma 2, 3 cmos standby current ( cs =v cc -0.2v) i cc2 0.5 2 ma 2, 3 input leakage current (any input) i il -1 +1 a cei input leakage i cei -160 +1 a 15 psel input leakage i psel +1 -160 a 16 output leakage current i ol +160 -1 a 8 output logic 1 voltage (i out = 0.4 ma) v oh 2.4 v output logic 0 voltage (i out = 0.8 ma) v ol 0.4 v output voltage v cco1 v cc -0.3 v4 output current i cco1 50 ma 4 power-fail trip point v pf 2.5 2.6 2.7 v 5 output voltage v cco2 v bat -0.3 v6 output current i cco2 100 a 6 battery leakage osc on i bat1 500 1000 na battery leakage osc off i bat2 50 150 na 17 i/o leakage i lo -1 +1 a 7 pwr output @ 0.4v i olpwr 4ma 1 cei to ceo impedance z ce 120 12 rtc ac timing characteristics over the operating range (3v) parameter symbol min typ max units notes cycle time t cyc 915 dc ns pulse width, rd / wr low pw rwl 375 ns pulse width, rd / wr high pw rwh 450 ns input rise and fall time t r , t f 30 ns chip select setup time before wr , or rd t cs 75 ns chip select hold time t ch 0ns read data hold time t dhr 10 120 ns write data hold time t dhw 0ns muxed address valid time to ale fall t asl 90 ns muxed address hold time from ale fall t ahl 30 ns rd or wr high setup to ale rise t asd 30 ns pulse width ale high pw ash 180 ns ale low setup to rd or wr fall t ased 120 ns output data delay time from rd t ddr 20 370 ns 9 data setup time t dsw 180 ns irq release from rd t ird 2 s cei to ceo delay t ced 20 ns
ds1689/DS1693 25 of 32 ds1689/DS1693 bus timing for read cycle to rtc rtc ac timing characteristics over the operating range (5v) parameter symbol min typ max units notes cycle time t cyc 305 dc ns pulse width, rd / wr low pw rwl 125 ns pulse width, rd / wr high pw rwh 150 ns input rise and fall time t r , t f 30 ns chip select setup time before wr , or rd t cs 20 ns chip select hold time t ch 0ns read data hold time t dhr 10 80 ns write data hold time t dhw 0ns muxed address valid time to ale fall t asl 30 ns muxed address hold time from ale fall t ahl 10 ns rd or wr high setup to ale rise t asd 25 ns pulse width ale high pw ash 60 ns ale low setup to rd or wr fall t ased 40 ns output data delay time from rd t ddr 20 120 ns 9 data setup time t dsw 100 ns irq release from rd t ird 2 s cei to ceo delay t ced 10 ns
ds1689/DS1693 26 of 32 ds1689/DS1693 bus timing for write cycle to rtc and rtc registers power-up condition 3-volt operation
ds1689/DS1693 27 of 32 power-down condition 3-volt operation power-up condition 5.0-volt operation power-down condition 5.0-volt operation
ds1689/DS1693 28 of 32 power-up power-down timi ng 5-volt operation (t a = 25 c) parameter symbol min typ max units notes cs high to power-fail t pf 0ns recovery at power-up t rec 150 ms v cc slew rate power-down t f 4.0 v cc 4.5v 300 s v cc slew rate power-down t fb 3.0 v cc 4.0v 10 s v cc slew rate power-up t r 4.5v v cc 4.0v 0 s expected data retention t dr 10 years 13, 14 power-up power-down timi ng 3-volt operation (t a = 25 c) parameter symbol min typ max units notes cs high to power-fail t pf 0ns recovery at power-up t rec 150 ms v cc slew rate power-down t f 2.5 v cc 3.0v 300 s v cc slew rate power-up t r 3.0v v cc 2.5v 0 s expected data retention t dr 10 years 13, 14 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery back-up mode. capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 12 pf output capacitance c out 12 pf wake-up/kickstart timing (t a = 25 c) parameter symbol min typ max units notes kickstart input pulse width t kspw 2 s wake-up/kickstart power-on timeout t poto 2 seconds 10
ds1689/DS1693 29 of 32 wake-up/kickstart timing note: time intervals shown above are refere nced in wake-up/kickstart section. * this condition can occur when the device is operated in 3-volt mode.
ds1689/DS1693 30 of 32 notes: 1. all voltages are referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. value for voltage and currents is from the v cci input pin to the v cco pin. 5. write protection trip point occurs durin g power fail prior to switchover from v cc to v bat . 6. value for voltage and currents is from the v bat input pin to the v cco pin. 7. applies to the ad0-ad7 pins, and the sqw pin when each is in a high impedance state. 8. the irq pin is open drain. 9. measured with a load of 50 pf + 1 ttl gate. 10. wakeup kickstart timeout generated only when the oscillator is enabled and the countdown chain is not reset. 11. v sw is determined by the larger of v bat and v baux . 12. z ce is an average input to output impedan ce as the input is swept from gnd to v cci and less than 4 ma is forced through z ce . 13. the DS1693 will keep time to an accuracy of 1 minute per month during data retention time for the period of t dr . 14. t dr is the amount of time that the internal battery can power the internal oscillator and internal registers of the DS1693. as such, t dr is specified with v cco floating. if v cco is powering an external sram, an auxiliary battery must be connected to the v baux pin. the auxiliary battery should be sized such that it can power the external sram for the t dr period.
the cei pin has an internal pull-up of 60 k . 16. the psel pin has an internal pull-down of 60 k
17. for industrial grade parts, i bat (with osc off) limit increases to 250 na. 18. real-time clock modules can be successfully processed through conv entional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post-solder cleaning with water wash ing techniques is acceptable, provided that ultrasonic vibration is not used.
ds1689/DS1693 31 of 32 ds1689s 28-pin soic pkg 28-pin dim min max a in. mm 0.697 17.70 0.728 18.50 b in. mm 0.324 8.23 0.350 8.90 c in. mm 0.087 2.20 0.118 3.00 d in. mm 0.016 0.40 0.050 1.27 e in. mm 0.002 0.05 0.014 0.35 f in. mm 0.100 2.55 0.120 3.05 g in. mm 0.050 bsc 1.27 bsc h in. mm 0.453 11.50 0.500 12.70 j in. mm 0.006 0.14 0.013 0.32 k in. mm 0.014 0.35 0.020 0.50
ds1689/DS1693 32 of 32 DS1693 28-pin 740-mil module pkg 28-pin dim min max a in. mm 1.520 38.61 1.540 39.12 b in. mm 0.695 17.65 0.740 18.80 c in. mm 0.350 8.89 0.375 9.52 d in. mm 0.100 2.54 0.130 3.30 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.110 2.79 0.140 3.56 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53 note: pins 2, 3, 19 and 23 are missing by design.

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